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19-2006; Rev 0; 5/01
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
General Description
The MAX105 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX105 converts the analog signals of both I and Q components to digital outputs at 800Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 200MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.25 LSB. The MAX105 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees phase. Dynamic performance is 36.4dB signal-to-noise plus distortion (SINAD) with a 200MHz analog input signal and a sampling speed of 800MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles. In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX105 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40C to +85C) temperature range. For a lower-speed, 400Msps version of the MAX105, please refer to the MAX107 data sheet. o Two Matched 6-Bit, 800Msps ADCs o Excellent Dynamic Performance 36.4dB SINAD at fIN 200MHz and fCLK 800MHz o Typical INL and DNL: 0.25LSB o Channel-to-Channel Phase Matching: 0.2 o Channel-to-Channel Gain Matching: 0.04dB o 6:12 Demultiplexer reduces the Data Rates to 400MHz o Low Error Rate: 1016 Metastable States at 800Msps o LVDS Digital Outputs in Two's Complement Format
Features
MAX105
Ordering Information
PART MAX105ECS TEMP. RANGE -40C to +85C PIN-PACKAGE 80-Pin TQFP-EP
Block Diagram
I PRIMARY PORT I ADC I AUXILIARY PORT
Applications
VSAT Receivers WLANs Test Instrumentation Communications Systems
MAX107
REF
Q PRIMARY PORT Q ADC Q AUXILIARY PORT
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
ABSOLUTE MAXIMUM RATINGS
AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V OVCCI and OVCCQ to OGND ...................................-0.3V to +4V AGND to OGND ................................................... -0.3V to +0.3V P0I to P5I and A0I to A5I DREADY+, DREADY- to OGNDI .............-0.3V to OVCCI+0.3V P0Q to P5Q, A0Q to A5Q DOR+ and DOR- to OGNDQ ................-0.3V to OVCCQ+0.3V REF to AGNDR...........................................-0.3V to AVCCR+0.3V Differential Voltage Between INI+ and INI- ....................-2V, +2V Differential Voltage Between INQ+ and INQ-.................-2V, +2V Differential Voltage Between CLK+ and CLK- ...............-2V, +2V Maximum Current Into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70C) 80-Pin TQFP (derate 44mW/C above +70C)..................3.5W Operating Temperature Range MAX105ECS .....................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead temperature (soldering, 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Voltage Offset Matching Between ADCs Input Open-Circuit Voltage Input Open-Circuit Voltage Matching Common Mode Input Voltage Range (Note 3) Full-Scale Analog Input Voltage Range (Note 4) Input Resistance Input Capacitance Input Resistance Temperature Coefficient Full-Power Analog Input BW REFERENCE OUTPUT Reference Output Resistance Reference Output Voltage RREF REF Referenced to AGNDR ISOURCE = 500A 2.45 5 2.50 2.55 V VCM VFSR RIN CIN TCRIN FPBW-0.5dB RES INL DNL VOS OM VAOC (VINI+ - VIN-) - (VINQ+ - VINQ-) Signal + Offset w.r.t. AGND 1.85 0.76 1.7 0.8 2 1.5 150 400 No missing codes guaranteed (Note 2) (Note 2) 6 -1 -1 -1 -0.5 2.4 0.2 0.25 0.25 0.1 2.5 1 1 1 0.5 2.6 7.5 3.05 0.84 Bits LSB LSB LSB LSB V mV V Vp-p k pF ppm/C MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUTS (INI+, INI-, INQ+, INQ-)
2
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
PARAMETER CLOCK INPUTS (CLK+, CLK-) Clock Input Resistance Clock Input Resistance Temperature Coefficient Minimum Clock Input Amplitude Differential Output Voltage Change in Magnitude of VOD Between "0" and "1" States Steady-State Common Mode Output Voltage Change in Magnitude of VOC Between "0" and "1" States Differential Output Resistance Output Current DYNAMIC SPECIFICATION Effective Number of Bits (Note 8) fIN = 200.018MHz at -0.5dB FS (Note 9) ENOB fIN = 400.134MHz at -0.5dB FS fIN = 200.018MHz at -0.5dB FS (Note 9) SNR fIN = 400.134MHz at -0.5dB FS fIN = 200.018MHz at -0.5dB FS (Note 9) THD fIN = 400.134MHz at -0.5dB FS fIN = 200.018MHz at -0.5dB FS (Note 9) Spurious-Free Dynamic Range SFDR fIN = 400.134MHz at -0.5dB FS Differential Single-ended Differential Differential Single-ended Differential Differential Single-ended Differential Differential Single-ended Differential 41 35 5.4 5.8 5.75 5.65 37 36.7 36.5 -44.5 -44.5 -41 45 45 41.5 dB -41 dBc dB Bits Short output together Short to OGNDI = OGNDQ VOD VOD VOC(SS) VOC 80 2.5 25 1.125 RCLK TCRCLK 500 CLK+ and CLK- to AGND 5 150 k ppm/C mVp-p SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX105
LVDS OUTPUTS (P0I TO P5I, P0Q TO P5Q, A0I TO A5I, A0Q TO A5Q, DREADY+, DREADY-, DOR+, DOR-) 247 400 25 1.375 25 160 mV mV V mV mA
Signal-to-Noise Ratio (Notes 10, 11)
Total Harmonic Distortion (Note 11)
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
PARAMETER Signal-to-Noise Plus Distortion Ratio SYMBOL CONDITIONS fIN = 200.018MHz at -0.5dB FS (Note 9) SINAD fIN = 400.134MHz at -0.5dB FS TTIMD XTLK GM PM Differential Single-ended Differential MIN 34 TYP 36.4 36.1 35.2 -52 -70 -0.3 -2 0.04 0.2 +0.3 +2 dBc dB dB deg Clock Cycles V V 320 510 mA mA W dB dB dB MAX UNITS
Two-Tone Intermodulation Crosstalk Between ADCs Gain Match Between ADCs Phase Match Between ADCs Metastable Error Rate POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current Output Supply Current Analog Power Dissipation Common-Mode Rejection Ratio Power-Supply Rejection Ratio TIMING CHARACTERISTICS Maximum Sample Rate Clock Pulse Width Low Clock Pulse Width High Aperture Delay Aperture Jitter CLK-to-DREADY Propagation Delay DREADY-to-DATA Propagation Delay
fIN1 = 124.1660MHz, fIN2 = 126.1260MHz at -7dBFS fINI = 200.0180MHz, fINQ = 210.0140MHz at -0.5dB FS (Note 12) (Note 12)
Less than 1 in 1016
AVCC_ OVCC_ ICC OICC PDISS CMRR PSRR
AVCC = AVCCI = AVCCQ = AVCCR OVCC I = OVCC Q ICC = AICCR + AICCI + AICCQ + AICC OICC = OICC I + OICC Q VIN_+ = VIN_- = 0.1V (Note 6) AVCC = AVCC I = AVCC Q = AVCC R = +4.75V to +5.25V (Note 7) 40 40
5 5% 3.3 10% 250 400 2.6 60 57
fMAX tPWL tPWH tAD tAJ tPD1 tPD2 (Note 13) (Notes 5, 13)
800 0.56 0.56 100 1.5 1.5 0 120 300
Msps ns ns ps psRMS ns ps
4
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, CL= 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
PARAMETER DREADY Duty Cycle LVDS Output Rise-Time LVDS Output Fall-Time LVDS Differential Skew DREADY Rise-Time DREADY Fall-Time Primary Port Pipeline Delay Auxiliary Port Pipeline Delay tRDATA tFDATA tSKEW1 tRDREADY tFDREADY tPDP tPDA SYMBOL (Notes 5, 13) 20% to 80% (Notes 5, 13) 20% to 80% (Notes 5, 13) Any differential pair Any two LVDS output signals except DREADY 20% to 80% (Notes 5, 13) 20% to 80% (Notes 5, 13) 200 200 5 6 CONDITIONS MIN 47 200 200 <65 <100 500 500 TYP MAX 53 500 500 UNITS % ps ps ps ps ps ps Clock Cycles Clock Cycles
MAX105
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
NL and DNL is measured using a sine-histogram method. Input offset is the voltage required to cause a transition between codes 0 and -1. Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage level does not matter. The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algorithm (e.g. FFT). Guaranteed by design and characterization. Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the commonmode voltage expressed in dB. Measured with analog power supplies tied to the same potential. Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range. The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record. Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal. The worst case number is presented. Harmonic distortion components two through five are excluded from the noise. Harmonic distortion components two through five are included in the total harmonic distortion specification. Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input frequency of fIN = 200.0180 MHz. Measured with a differential probe, 1pF capacitance.
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
Typical Operating Characteristics
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
8192-POINT FFT, DIFFERENTIAL INPUT
MAX105 toc01
8192-POINT FFT, DIFFERENTIAL INPUT
-10 -20 AMPLITUDE (dB FS) -30 -40 -50 -60 -70 -80 -90 -100 fIN = 124.999MHz AIN = -0.5dB FS
MAX105 toc02
8192-POINT FFT, DIFFERENTIAL INPUT
-10 -20 AMPLITUDE (dB FS) -30 -40 -50 -60 -70 -80 -90 -100 fIN = 400.124MHz AIN = -0.5dB FS
MAX105 toc03
0 -10 -20 AMPLITUDE (dB FS) -30 -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100 120 fIN = 125.146MHz AIN = -0.5dB FS
0
0
140
0
40
80
120
160
200
0
70
140
210
280
350
420
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD (8192-POINT RECORD), DIFFERENTIAL INPUT
MAX105 toc04
SNR vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT
-1dB FS 35 30 AMPLITUDE (dB) 25 20 15 10 5 0 -6dB FS AMPLITUDE (dB) -12dB FS
MAX105 toc05
SINAD vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT
35 30 25 20 15 10 5 0 10M 100M 1G 10G -1dB FS -6dB FS -12dB FS
MAX105 toc06
0 -10 -20 AMPLITUDE (dB FS) -30 -40 -50 -60 -70 -80 -90 -100 0 80 160 240 320 fIN1 fIN2 fN1 = 124.166MHz fIN2 = 126.126MHz AIN = -7dB FS
40
40
400
10M
100M
1G
10G
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (Hz)
ANALOG INPUT FREQUENCY (Hz)
THD vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT
MAX105 toc07
SFDR vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL INPUT
MAX105 toc08
FULL-POWER INPUT BANDWIDTH SINGLE-ENDED INPUT
MAX105 toc09
-20 -25 -30 AMPLITUDE (dB) -35 -40 -45 -50 -55 -60 10M 100M 1G -6dB FS -12dB FS
60 55 50 AMPLITUDE (dB) 45 40 35 30 25 20 15 10 -12dB FS -6dB FS -1dB FS
1
0
GAIN (dB) 100M 1G 10G
-1
-2
-1dB FS
-3
-4 10M 10M 100M 1G 10G ANALOG INPUT FREQUENCY (Hz) ANALOG INPUT FREQUENCY (Hz)
10G
ANALOG INPUT FREQUENCY (Hz)
6
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
Typical Operating Characteristics (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
SNR vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT
MAX105 toc10
fIN = 199.8535MHz 36 SNR (dB)
MAX105 toc11
fIN = 199.8535MHz 36 SINAD (dB)
fIN = 199.8535MHz -38 THD (dB)
32
32
-42
28
28
-46
24 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ANALOG INPUT POWER (dB FS)
24 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ANALOG INPUT POWER (dB FS)
-50 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ANALOG INPUT POWER (dB FS)
SFDR vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT
MAX105 toc13
SNR vs. TEMPERATURE
MAX105 toc14
SINAD vs. TEMPERATURE
fIN = 199.8535MHz 40 SINAD (dB)
MAX105 toc15
50 fIN = 199.8535MHz 48 46 SFDR (dB) 44 42 40 38 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 ANALOG INPUT POWER (dB FS)
45 fIN = 199.8535MHz 41
42
SNR (dB)
37
38
33
36
29
34
25 -40 -15 10 35 60 85 TEMPERATURE (C)
32 -40 -15 10 35 60 85 TEMPERATURE (C)
THD vs. TEMPERATURE
MAX toc16
SFDR vs. TEMPERATURE
MAX105 toc17
SNR vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS)
fIN = 202.346MHz 38 AMPLITUDE (dB)
MAX105 toc18
-38 fIN = 199.8535MHz -42
55 fIN = 199.8535MHz 51
40
SFDR (dB)
THD (dB)
47
36
-46
43
34
-50
39
32
-54 -40 -15 10 35 60 85 TEMPERATURE (C)
35 -40 -15 10 35 60 85 TEMPERATURE (C)
30 400 500 600 700 800 900 CLOCK FREQUENCY (MHz)
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7
MAX105 toc12
40
SINAD vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT
40 -34
THD vs. ANALOG INPUT POWER, DIFFERENTIAL INPUT
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
Typical Operating Characteristics (continued)
(AVCC = AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ = 0, fCLK = 802.816MHz, differential input at -0.5dB FS, CL = 1F to AGND at REF, RL = 100 1% applied to digital LVDS outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C)
SINAD vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc19
THD vs. CLOCK FREQUENCY, DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc20
ENOB vs. ANALOG SUPPLY VOLTAGE, DIFFERENTIAL INPUT (-1dB FS)
fIN = 202.0761MHz 5.9 ENOB (Bits)
MAX105 toc21
40 fIN = 202.346MHz 38 AMPLITUDE (dB)
-40 fIN = 202.346MHz -43 AMPLITUDE (dB)
6.0
36
-46
5.8
34
-49
5.7
32
-52
5.6
30 400 500 600 700 800 900 CLOCK FREQUENCY (MHz)
-55 400 500 600 700 800 900 CLOCK FREQUENCY (MHz)
5.5 4.5 4.7 4.9 5.1 5.3 5.5 ANALOG SUPPLY VOLTAGE (V)
SFDR vs. ANALOG SUPPLY VOLTAGE, DIFFERENTIAL INPUT (-1dB FS)
MAX105 toc22
INL vs. DIGITAL OUTPUT CODE
MAX105 toc23
DNL vs. DIGITAL OUTPUT CODE
MAX105 toc24
50 fIN = 202.0761MHz 49
0.30 0.20 0.10
0.40
0.20 DNL (LSB) 0 8 16 24 32 40 48 56 64 INL (LSB)
SFDR (dB)
48
0
0
47
-0.10 46 -0.20 -0.20 -0.30 4.5 4.7 4.9 5.1 5.3 5.5 ANALOG SUPPLY VOLTAGE (V) DIGITAL OUTPUT CODE -0.40 0 8 16 24 32 40 48 56 64 DIGITAL OUTPUT CODE
45
REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
MAX toc25
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX105 toc26
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX105 toc27
2.510
300 ANALOG SUPPLY CURRENT (mA)
300 ANALOG SUPPLY CURRENT (mA)
REFERENCE VOLTAGE (V)
2.506
280
280
2.502
260
260
2.498
240
240
2.494
220
220
2.490 4.5 4.7 4.9 5.1 5.3 5.5 ANALOG SUPPLY VOLTAGE (V)
200 4.5 4.7 4.9 5.1 5.3 5.5 ANALOG SUPPLY VOLTAGE (V)
200 -40 -15 10 35 60 85 TEMPERATURE (C)
8
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
Pin Description
PIN 1, 20 2 3 4 5, 8 6 7 9 10 11 12 13, 16 14 15 17, 18 19 21 22 23 24 25 26 27 28 29, 35 30, 36 NAME T.P. REF AVCCR AGNDR AGNDI INIINI+ AVCCI CLK+ CLKAVCCQ AGNDQ INQ+ INQAGND AVCC A5Q+ A5QP5Q+ P5QA4Q+ A4QP4Q+ P4QOVCCQ OGNDQ Test Point. Do not connect. Reference Output Analog Reference Supply. Supply voltage for the internal bandgap reference. Bypass to AGNDR with 0.01F in parallel with 47pF for proper operation. Reference, Analog Ground. Connect to AGND for proper operation. I-Channel, Analog Ground. Connect to AGND for proper operation. I-Channel, Differential Input. Negative terminal. I Channel, Differential Input. Positive terminal. I-Channel, Analog Supply. Supplies I-channel common-mode buffer, pre-amplifier and quantizer. Bypass to AGNDI with 0.01F in parallel with 47pF for proper operation. Sampling Clock Input Complementary Sampling Clock Input Q-Channel, Analog Supply. Supplies Q-channel common-mode buffer, pre-amplifier and quantizer. Bypass to AGNDQ with 0.01F in parallel with 47pF for proper operation. Q-Channel, Analog Ground. Connect to AGND for proper operation. Q-Channel, Differential Input. Positive terminal. Q-Channel, Differential Input. Negative terminal. Analog Ground Analog Supply. Bypass to AGND with 0.01F in parallel with 47pF for proper operation. Auxiliary Output Data Bit 5 (MSB), Q-Channel Complementary Auxiliary Output Data Bit 5 (MSB), Q-Channel Primary Output Data Bit 5 (MSB), Q-Channel Complementary Primary Output Data Bit 5 (MSB), Q-Channel Auxiliary Output Data Bit 4, Q-Channel Complementary Auxiliary Output Data Bit 4, Q-Channel Primary Output Data Bit 4, Q-Channel Complementary Primary Output Data Bit 4, Q-Channel Q-Channel Outputs, Digital Supply. Supplies Q-channel output drivers and DOR logic. Bypass to OGND with 0.01F in parallel with 47pF for proper operation. Q-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board for proper operation. FUNCTION
MAX105
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
Pin Description (continued)
PIN 31 32 33 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 NAME A3Q+ A3QP3Q+ P3QA2Q+ A2QP2Q+ P2QA1Q+ A1QP1Q+ P1QA0Q+ A0QP0Q+ P0QDOR+ DORDREADYDREADY+ P0IP0I+ A0IA0I+ P1IP1I+ A1IA1I+ P2IAuxiliary Output Data Bit 3, Q-Channel Complementary Auxiliary Output Data Bit 3, Q-Channel Primary Output Data Bit 3, Q-Channel Complementary Primary Output Data Bit 3, Q-Channel Auxiliary Output Data Bit 2, Q-Channel Complementary Auxiliary Output Data Bit 2, Q-Channel Primary Output Data Bit 2, Q-Channel Complementary Primary Output Data Bit 2, Q-Channel Auxiliary Output Data Bit 1, Q-Channel Complementary Auxiliary Output Data Bit 1, Q-Channel Primary Output Data Bit 1, Q-Channel Complementary Primary Output Data Bit 1, Q-Channel Auxiliary Output Data Bit 0 (LSB), Q-Channel Complementary Auxiliary Output Data Bit 0 (LSB), Q-Channel Primary Output Data Bit 0 (LSB), Q-Channel Complementary Primary Output Data Bit 0 (LSB), Q-Channel Complementary LVDS Out-Of-Range Bit LVDS Out-of-Range Bit Complementary Data-Ready Clock Data Ready Clock Complementary Primary Output Data Bit 0 (LSB), I-Channel Primary Output Data Bit 0 (LSB), I-Channel Complementary Auxiliary Output Data Bit 0 (LSB), I-Channel Auxiliary Output Data Bit 0 (LSB), I-Channel Complementary Primary Output Data Bit 1, I-Channel Primary Output Data Bit 1, I-Channel Complementary Auxiliary Output Data Bit 1, I-Channel Auxiliary Output Data Bit 1, I-Channel Complementary Primary Output Data Bit 2, I-Channel FUNCTION
10
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
Pin Description (continued)
PIN 62 63 64 65, 72 66, 71 67 68 69 70 73 74 75 76 77 78 79 80 NAME P2I+ A2IA2I+ OVCCI OGNDI P3IP3I+ A3IA3I+ P4IP4I+ A4IA4I+ P5IP5I+ A5IA5I+ Primary Output Data Bit 2, I-Channel Complementary Auxiliary Output Data Bit 2, I-Channel Auxiliary Output Data Bit 2, I-Channel I-Channel Outputs, Digital Supply. Supplies I-channel output drivers and DREADY circuit. Bypass to OGND with 0.01F in parallel with 47pF for proper operation. I-Channel Outputs, Digital Ground. Connect to designated digital ground (OGND) on PC board for proper operation. Complementary Primary Output Data Bit 3, I-Channel Primary Output Data Bit 3, I-Channel Complementary Auxiliary Output Data Bit 3, I-Channel Auxiliary Output Data Bit 3, I-Channel Complementary Primary Output Data Bit 4, I-Channel Primary Output Data Bit 4, I-Channel Complementary Auxiliary Output Data Bit 4, I-Channel Auxiliary Output Data Bit 4, I-Channel Complementary Primary Output Data Bit 5, I-Channel Primary Output Data Bit 5, I-Channel Complementary Auxiliary Output Data Bit 5, I-Channel Auxiliary Output Data Bit 5, I-Channel FUNCTION
MAX105
Detailed Description
The MAX105 is a dual, +5V, 6-bit, 800Msps flash analog-to-digital converter (ADC), designed for highspeed, high-bandwidth I&Q digitizing. Each ADC (Figure 1) employs a fully differential, wide bandwidth input stage, 6-bit quantizers and a unique encoding scheme to limit metastable states to typically one error per 1016 clock cycles, with no error exceeding a maximum of 1LSB. An integrated 6:12 output demultiplexer simplifies interfacing to the part by reducing the output data rate to one-half the sampling clock rate. The MAX105 outputs data in LVDS two's complement format. When clocked at 800Msps, the MAX105 provides a typical signal-to-noise plus distortion (SINAD) of 36.4dB with a 200MHz input tone. The analog input of the MAX105 is designed for differential or single-ended use with a 400mV full-scale input range. In addition, the
MAX105 features an on-board +2.5V precision bandgap reference, which is scaled to meet the analog input full-scale range.
Principle of Operation
The MAX105 employs a flash or parallel architecture. The key to this high-speed flash architecture is the use of an innovative, high-performance comparator design. Each quantizer and downstream logic translates the comparator outputs into 6-bit, parallel codes in two's complement format and passes them on to the internal 6:12 demultiplexer. The demultiplexer enables the ADCs to provide their output data at half the sampling speed on primary and auxiliary ports. LVDS data is available at speeds of up to 400MHz per output port.
Input Amplifier Circuits
As with all ADCs, if the input waveform is changing rapidly during conversion, effective number of bits (ENOB), signal-to-noise plus distortion (SINAD), and
11
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
DREADY+/DREADY-
MAX105
INI+ PRE-AMP INI2k CM BUFFER 1:2 REFERENCE DOR 2k INQ+ PRE-AMP INQCM BUFFER REF Q ADC
PRIMARY DATA PORT P0I-P5I AUXILIARY DATA PORT A0I-A5I AVCC 10k
P0I+/P0IP5I+/P5IA0I+/A0IA5I+/A5I-
I ADC REF
CLK+ CLK10k
PRIMARY DATA PORT P0Q-P5Q AUXILIARY DATA PORT A0Q-A5Q
P0Q+/P0QP5Q+/P5QA0Q+/A0QA5Q+/A5Q-
REF
DOR+/DOR-
Figure 1. MAX105 Flash Converter Architecture
signal-to-noise ratio (SNR) specifications will degrade. The MAX105's on-board, wide-bandwidth input amplifiers (I&Q) reduce this effect significantly, allowing precise digitizing of fast analog data at high conversion rates. The input amplifiers buffer the input signal and allow a full-scale signal input range of 400mV (800mVp-p).
OVCCI
OVCCI P0I+ - P5I+ A0I+ - A5I+ OVCCI P0I- - P5IA0I- - A5I-
Internal Reference
The MAX105 features an integrated, buffered +2.5V precision bandgap reference. This reference is internally scaled to match the analog input range specification of 400mV. The data converter's reference output (REF) can source up to 500A. REF should be buffered, if used to supply external devices.
55
55
LVDS Digital Outputs
The MAX105 provides data in two's complement format to differential LVDS outputs. A simplified circuit schematic of the LVDS output cells is shown in Figure 2. All LVDS outputs are powered from separate I-channel OVCCI and Q-channel OVCCQ (Q-channel) power supplies, which may be operated at +3.3V 10%. The
12
MAX105
Figure 2. Simplified LVDS Output Model
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
Table 1. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog Input
IN-PHASE INPUTS (INI+, INQ+) > +400mV + VREF +400mV - 0.5LSB + VREF 0V + VREF -400mV + 0.5LSB + VREF < -400mV + VREF INVERTED INPUTS (INI-, INQ-) AC - Coupled to AGND_ AC - Coupled to AGND_ AC - Coupled to AGND_ AC - Coupled to AGND_ AC - Coupled to AGND_ OUT-OF-RANGE BIT (DOR+, DOR-) 1 0 0 0 1 OUTPUT CODE 011111 011111 000000/111111 100000 100000
MAX105
Table 2. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
IN-PHASE INPUTS (INI+, INQ+) >+200mV + VREF +200mV - 0.25LSB + VREF 0V + VREF -200mV + 0.25LSB + VREF <-200mV + VREF INVERTED INPUTS (INI-, INQ-) <-200mV + VREF -200mV + 0.25LSB + VREF 0V + VREF +200mV - 0.25LSB + VREF >+200mV + VREF OUT-OF-RANGE BIT (DOR+, DOR-) 1 0 0 0 1 OUTPUT CODE 011111 011111 000000/111111 100000 100000
MAX105 LVDS-outputs provide a typical 270mV voltage swing around a common mode voltage of roughly +1.2V, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100.
ended operation allows for an input amplitude of 800mVp-p, centered around VREF.
Differential Analog Inputs
To obtain +FS digital outputs with differential input drive (Table 2), 400mV must be applied between INI+ (INQ+) and INI- (INQ-). Midscale digital output codes occur when there is no voltage difference between INI+ (INQ+) and INI- (INQ-). For a -FS digital output code both in-phase (INI+, INQ+) and inverted input (INI-, INQ-) must see -400mV.
Out-Of-Range Operation
A single output pair (DOR+, DOR-) is provided to flag an out-of-range condition, if either the I or Q channel is out-of-range, where out-of-range is above +FS or below -FS. It features the same latency as the ADCs output data and is demultiplexed in a similar fashion. With a 800MHz system clock, DOR+ and DOR- are clocked at up to 400MHz.
Single-Ended to Differential Conversion Using a Balun
An RF balun (Figure 3) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX105 for optimum performance. At higher frequencies, the MAX105 provides better SFDR and THD with fully differential input signals over single-ended input signals. In differential input mode, even-order harmonics are suppressed and each input requires only half the signal-swing compared to singleended mode.
Applications Information
Single-Ended Analog Inputs
The MAX105 is designed to work at full-speed for both single-ended and differential analog inputs without significant degradation in its dynamic performance. Both input channels I (INI+, INI-) and Q (INQ+, INQ-) have 2k impedance and allow for AC- and DC-coupled input signals. In a typical DC-coupled single-ended configuration (Table 1), the analog input signals enter the analog input amplifier stages at the in-phase-input pins INI+/INQ+, while the inverted phase input INI/INQ- pins are AC-coupled to AGNDI/AGNDQ. Single-
Clock Input
The MAX105 features clock inputs designed for either single-ended or differential operation with very flexible input drive requirements. The clock inputs (AC- or DCcoupled) provide a 5k input impedance to AVCC/2
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
50 100pF D 0 SIGNAL SOURCE A 50 180 0 0 B AGND CLK+, INI+, INQ+
tude) to +10dBm (2VP-P clock signal amplitude). The MAX105 dynamic performance specifications are determined by a single-ended clock drive of -2dBm (500mVp-p clock signal amplitude). To avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dBm. Differential Clock (Sine-Wave Drive) The advantages of differential clock drive (Figure 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. Refer to Single-Ended Clock Inputs (Sine-Wave Drive) for proper input amplitude requirements.
50* AGND
C 100pF CLK-, INI-, INQ50 TRANSMISSION LINES 50 100pF AGND *TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50 TO AGND) ON A BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS. 50 TO 50-TERMINATED SIGNAL SOURCE OR BALUM AGND CLK+, INI+, INQ+ CLK-, INI-, INQ-
50
100pF
Figure 3. Single-Ended to Differential Conversion Using a Balun
AGND
and are internally buffered with a preamplifier to ensure proper operation of the converter even with smallamplitude sine-wave sources. The MAX105 was designed for single-ended, low-phase noise sine wave clock signals with as little as 500mV P-P amplitude (-2dBm). Single-Ended Clock (Sine-Wave Drive) Excellent performance is obtained by AC- or DC-coupling a low-phase noise sine-wave source into a single clock input (Figure 4). Essentially, the dynamic performance of the converter is unaffected by clock-drive power levels from -2dBm (500mVp-p clock signal ampli-
Figure 5. Differential AC-Coupled Input Drive (CLK, INI, INQ)
LVDS, ECL and PECL Clock The innovative input architecture of the MAX105 clock also allows these inputs to be driven by LVDS-, ECL-, or PECL-compatible input levels, ranging from 500mVp-p to 2Vp-p (Figure 6).
50 TRANSMISSION LINES 100pF SIGNAL SOURCE INPUT
CLK-, INI-, INQCLK+, INI+, INQ+
100 100pF
50 100pF FROM SIGNAL SOURCE 100pF
AGND CLK+, INI+, INQ+ CLK-, INI-, INQLVDS LINE DRIVER
Figure 6. LVDS Input Drive (CLK, INI, INQ)
AGND
Timing Requirements
The MAX105 features a 6:12 demultiplexer, which reduces the output data rate (including DREADY and DOR signals) to one-half of the sample clock rate. The
Figure 4. Single-Ended Clock Input With AC-Coupled Input Drive (CLK, INI, INQ) 14
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
ADC SAMPLE MAX105 ADCs SAMPLE ON THE RISING EDGE OF CLK+ CLKCLK CLK+ DREADYDREADY DREADY+ AUXILIARY DATA PORT PRIMARY DATA PORT N N+2 N+4 N+6 N+8 N+10 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19
N+1
N+3
N+5
N+7
N+9
N+11
NOTE: THE LATENCY TO THE PRIMARY PORT IS FIVE CLOCK CYCLES, THE LATENCY TO THE AUXILIARY PORT IS SIX CLOCK CYCLES. BOTH PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
tPWH CLK+ CLKtPD1
tPWL
DREADY + DREADY tPD2 AUXILIARY PORT DATA
PRIMARY PORT DATA
MAX105
Figure 7. Output Timing Relationship Between CLK and DREADY Signals and Primary/Auxiliary Output Ports
demultiplexed outputs are presented in dual 6-bit two's complement format with two consecutive samples in the primary and auxiliary output ports on the rising edge of the data ready clock. The auxiliary data port always contains the older sample. The primary output always contains the most recent data sample, regardless of the DREADY clock phase. Figure 7 shows the timing and data alignment of the auxiliary and primary output ports in relationship with the CLK and DREADY signals. Data in the primary port is delayed by five clock cycles while data in the auxiliary port is delayed by six clock cycles.
Typical I/Q Application
Quadrature amplitude modulation (QAM) is frequently used in digital communication systems to increase channel capacity. A QAM signal is modulated in both amplitude and phase. With a demodulator, this QAM signal gets downconverted and separated in its inphase (I) and quadrature (Q) components. Both I&Q channels are digitized by an ADC at the baseband level in order to recover the transmitted information. Figure 8 shows a typical application circuit to directly tune L-band signals to baseband, incorporating a direct conversion tuner (MAX2108) and the MAX105 to digitize I&Q channels with excellent phase- and gainmatching. A front-end L-C filter is required for anti-aliasing purposes.
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
DREADY+/DREADYFROM PREVIOUS STAGE MAX2108 QUADRATURE DEMODULATOR PRIMARY DATA PORT P0I-P5I NYQUIST FILTER 2k PRE-AMP I ADC REF CM BUFFER 1:2 LO 90 REFERENCE DOR 2k NYQUIST FILTER CM BUFFER REF Q ADC PRIMARY DATA PORT P0Q-P5Q AUXILIARY DATA PORT A0Q-A5Q 10k AUXILIARY DATA PORT A0I-A5I AVCC 10k D S P
PRE-AMP
DOR+/DOR-
Figure 8. Typical I/Q Application
Grounding, Bypassing, and Board Layout
Grounding and power supply decoupling strongly influence the MAX105's performance. At 800MHz clock frequency and 6-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, ground connections, and adversely influence the dynamic performance of the ADC. In addition, the I&Q inputs may crosstalk through poorly designed decoupling circuits. Therefore, closely follow the grounding and power-supply decoupling guidelines in Figure 9. Maxim strongly recommends using a multilayer printed circuit board (PC board) with separate ground and power supply planes. Since the MAX105 has separate analog and digital ground connections (AGND, AGNDI, AGNDQ, AGNDR, OGNDI, and OGNDQ, respectively). The PC board should feature separate sections designated to analog (AGND) and digital (OGND), connected at only one point. Digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. Keep digital signals far away from the sensitive analog inputs, reference inputs,
16
and clock inputs. High-speed signals, including clocks, analog inputs, and digital outputs, should be routed on 50 microstrip lines, such as those employed on the MAX105EV kit. The MAX105 has separate analog and digital powersupply inputs: * AV CC = +5V 5%: Power supply for the analog input section of the clock circuit. * * * * * AVCCI = +5V 5%: Power supply for the I-channel common-mode buffer, pre-amp and quantizer. AVCCQ = +5V 5%: Power supply for the Q-channel common-mode buffer, pre-amp and quantizer. AVCCR = +5V 5%: Power supply for the on-chip bandgap reference. OVCCI = +3.3V 10%: Power supply for the I-channel output drivers and DREADY circuitry. OV CC Q = +3.3V 10%: Power supply for the Q-channel output drivers and DOR circuitry.
All supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. For best performance, bypass all power sup-
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
PC BOARD AVCC 10F 10nF
PC BOARD AGND
FERRITE-BEAD SUPPRESSORS OVCCI, OVCCQ 10F 10nF
4 x 10nF
PC BOARD OVCC
PC BOARD OGND AVCCR 10nF 47pF AGNDR AGNDR AVCCI 10nF 47pF AGNDI AGNDI AVCCQ 10nF 47pF AGNDQ AGNDQ AVCC 10nF 47pF AGND AGND OGNDQ OGNDQ AVCC OVCCQ 47pF 10nF OGNDQ OGNDQ OVCCQ AVCCQ OVCCQ 47pF 10nF OGNDI OGNDI OVCCQ AVCCI MAX105 OVCCI 47pF 10nF OGNDI OGNDI OVCCI AVCCR OVCCI 47pF 10nF OVCCI
NOTE: LOCATE ALL 47pF AND 10nF CAPACITORS, WHICH DECOUPLE AVCCI, AVCCQ, AVCCR, OVCCI, AND OVCCQ AS CLOSE AS POSSIBLE TO THE CHIP. IT IS ALSO RECOMMENDED TO CONNECT ALL ANALOG GROUND CONNECTIONS TO A COMMON ANALOG GROUND PLANE AND ALL DIGITAL GROUND CONNECTIONS TO ONE COMMON DIGITAL GROUND PLANE ON THE PC BOARD. A SIMILAR TECHNIQUE CAN BE USED FOR ALL ANALOG AND DIGITAL POWER SUPPLIES. AVCC = AVCCI = AVCCQ = AVCCR = +5V5% OVCCI = OVCCQ = +3.3V10%
Figure 9. MAX105 Decoupling, Bypassing and Grounding
plies to the appropriate ground with a 10F tantalum capacitor, to filter power supply noise, in parallel with a 0.1F capacitor. A combination of 0.01F in parallel with high quality 47pF ceramic chip capacitor located very close to the MAX105 device filters high frequency noise. A properly designed PC board (see MAX105EV Kit data sheet) allows the user to connect all analog supplies and all digital supplies together thereby requiring only two separate power sources. Decoupling
AV CC, AV CCI, AV CCQ and AV CCR with ferrite-bead suppressors prevents further crosstalk between the individual analog supply pins
Thermal Management
The MAX105 is designed for a thermally enhanced 80pin TQFP package, providing greater design flexibility, increased thermal efficiency and a low thermal junction-case (jc) resistance of 1.26C/W. In this pack17
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
DIE 80-PIN TQFP PACKAGE WITH EXPOSED PAD
BONDING WIRE
THERMAL LAND COPPER PLANE, 1oz. COPPER TRACE, 1oz. TOP LAYER GROUND PLANE AGND, DGND POWER PLANE
EXPOXY EXPOSED PAD COPPER TRACE, 1oz. PC BOARD
GROUND PLANE (AGND) 6 x 6 ARRAY OF THERMAL VIAS THERMAL LAND COPPER PLANE, 1oz.
MAX105
Figure 10. MAX105 Exposed Pad Package Cross-Section
age, the data converter die is attached to an exposed pad (EP) leadframe using a thermally conductive epoxy. The package is molded in a way, that this leadframe is exposed at the surface, facing the printed circuit board (PC board) side of the package (Figure 10). This allows the package to be attached to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (7.5mm x 7.5mm) does not only guarantee proper attachment of the chip, but can also be used for heat-sinking purposes. Designing thermal vias* into the land area and implementing large ground planes in the PC board design, further enhance the thermal conductivity between board and package. To remove heat from an 80-pin TQFP package efficiently, an array of 6 x 6 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) is required. Note: Efficient thermal management for the MAX105 is strongly depending on PC board and circuit design, component placement, and installation. Therefore, exact performance figures cannot be provided. However, the MAX105EV kit exhibits a typical ja of 18C/W. For more information on proper design techniques and recommendations to enhance the thermal performance of parts such as the MAX105, please refer to Amkor Technology's website at www.amkor.com.
*Connects the land pattern to internal or external copper planes. 18
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line is drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX105 are measured using the sine-histogram method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of greater than -1LSB guarantees no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter and Delay
Aperture uncertainties affect the dynamic performance of high-speed converters. Aperture jitter, in particular, directly influences SNR and limits the maximum slew rate (dV/dt) that can be digitized without significant error. Aperture jitter limits the SNR performance of the ADC, according to the following relationship: SNRdB = 20 x log10 [1 / (2 x x fIN x tAJ[RMS])], where fIN represents the analog input frequency and tAJ is the RMS aperture jitter. The MAX105's innovative
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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
Total Harmonic Distortion (THD)
CLKCLK+ tAW ANALOG INPUT tAD tAJ SAMPLING INSTANT
MAX105
THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:
MAX105
THD = 20 x log (V22 + V32 + V4 2 + V52 ) / V12 )
tAW: APERTURE WIDTH tAJ: APERTURE JITTER tAD: APERTURE DELAY
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Figure 11. Aperture Timing
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental to the RMS value of the next largest spurious component, excluding DC offset.
clock design limits aperture jitter to typically 1.5psRMS. Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -7dB full-scale and their envelope peaks at -1dB full-scale.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-Bits): SNRMAX[dB] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter (see Aperture Uncertainties). SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.
Chip Information
TRANSISTOR COUNT: 12,286
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency, amplitude, and sampling rate relative to an ideal ADC's quantization noise. For a full-scale input ENOB is computed from: ENOB = (SINAD - 1.76dB) / 6.02dB
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19
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier MAX105
Pin Configuration
71 OGNDI 72 OVCCI 66 OGNDI 65 OVCCI 80 A5I+ 78 P5I+ 76 A4I+ 74 P4I+ 70 A3I+ 68 P3I+ 64 A2I+ 62 P2I+ 79 A5I77 P5I75 A4I73 P4I69 A3I67 P3I63 A2I61 P2I60 59 58 57 56 55 54 53 52 51
T.P. REF AVCCR AGNDR AGNDI INIINI+ AGNDI AVCCI CLK+ CLKAVCCQ AGNDQ INQ+ INQAGNDQ AGND AGND AVCC T.P.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 27 36 21 22 24 25 28 29 30 31 32 34 35 38 23 33 37 39 40
A1I+ A1IP1I+ P1IA0I+ A0IP01+ P01DREADY+ DREADYDORDOR+ P0QP0Q+ A0QA0Q+ P1QP1Q+ A1QA1Q+
MAX105
50 49 48 47 46 45 44 43 42 41
OGNDQ
OGNDQ
A5Q+
P5Q+
A4Q+
P4Q+
OVCCQ
A3Q+
P3Q+
A2Q+
A5Q-
P5Q-
A4Q-
P4Q-
A3Q-
OVCCQ
20
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P2Q+
P3Q-
A2Q-
P2Q-
Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier
Package Information
MAX105
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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